Computing devices typically comprise a processor, memory, and an external memory controller to provide the processor as well as other components of the computing device with access to the memory. The performance of such computing devices is strongly influenced by the “memory read latency” and “memory write latency” of the computing device. In general, the “memory read latency” is the length of time between when the processor requests the external memory controller to retrieve data from the memory and when the external memory controller provides the processor with the requested data. Similarly, the “memory write latency” is generally the length of time between when the processor requests the external memory controller to write data to the memory and when the external memory controller indicates to the processor that the data has been or will be written to the memory.
One factor that contributes to the latency of memory transactions is the length of time the memory controller takes to decode the address of the memory transaction. The memory controller typically includes an address decoder that generates memory selects that correspond to a hierarchal arrangement of the memory. Since the address decoder typically supports numerous different hierarchal arrangements, the address decoder comprises non-trivial logic that consumes multiple clock cycles to decode the address.